An input/output (I/O) subsystem such as a DASD subsystem attached to a host CPU has a critical relationship to overall data processing system performance and availability. It is essential for high performance that the DASD subsystem provides rapid access to its DASDs for performing desired data processing operations. Furthermore, to maintain continuous operation of the system, the DASD subsystem should provide data integrity (no loss of data) and data availability (recovery in the case of a failure).
A conventional approach to these problems, for example, involves generating multiple copies of the same data and recording them onto multiple volumes of DASDs. For high data availability, these DASDs are preferably arranged to be independent of each other in respect to electrical power, mechanical movement and data transfer paths. In the case of a DASD failure, the data is available on another DASD that contains an identical copy of the data recorded on the failed DASD, thereby allowing the data processing system to continue its operations using such valid data. In the conventional approach, however, such recording of duplexed data takes place sequentially, thus imposing a performance penalty on the data processing system.
One example of this approach is disclosed in U.S. Pat. No. 4,453,215 to Reid, which is directed to a fault tolerant computer system comprising redundant components such as CPUs, buses, control units and DASDs. The system of this patent, while recording duplexed data onto a pair of DASDs, is not capable of concurrently recording the data onto these DASDs because this patent specifically recognizes that the DASDs do not operate in synchronism with one another. That is, the disclosed system necessarily incurs the performance penalty outlined below when the duplexed data is recorded onto the DASDs.
Another type of DASD subsystem, employed in a widely used data processing system such as the IBM System/370, provides several data transfer paths between a CPU and DASDs. A data transfer path is formed by the interconnection of the CPU to a control unit via a channel and the control unit to a DASD via a defined interface, as well known in the art. More than one data transfer path may be available to the same or different control units. Conventionally, the aforementioned approach is implemented such that multiple copies of the same data are recorded by accessing each DASD separately over a single data transfer path being formed by a channel and a control unit.
This implies that, in an implementation using a single data transfer path, the duplexed recording takes place truly sequentially because, in this case, separate chains of Channel Command Words (CCWs) are sequentially transferred from the CPU over the data transfer path to achieve such recording, i.e., DASDs are rendered to operate sequentially of one another. In the worst case, for each DASD accessed, time is spent sequentially for seek, rotational latency, and then data transmission.
In another implementation using multiple data transfer paths, even when the CPU attempts to record the duplexed data onto multiple DASDs concurrently, this does not always take place. The reasons for this problem are:
(1) Separate chains of CCWs, as described earlier, are asynchronously transferred from the CPU to multiple control units. PA1 (2) Data transfer paths to the DASDs are not necessarily available at the same time. For example, when a single copy of data is about to be recorded onto one of the DASDs, the data transfer path to another DASD may be busy with another operation. In this case, it is normally impossible to predict the precise time when the data transfer path to another DASD becomes free. PA1 (3) Rotational latency of one of the DASDs may be different from that of another DASD at a given time. This causes the multiple DASDs to record the same data at different times.
For these reasons, the approach so implemented does not allow the concurrent recordation of the duplexed data onto the multiple DASDs. Though the recordation of duplexed data is allowed in an overlapped manner in certain situations, there is no practical way to predict the degree of overlapping nor exact timing of such recording.
Thus, the overall performance of a data processing system using the conventional approach is significantly impaired. The conventional approach is disadvantageous in that, at the conclusion of recording the first copy, when its associated status information is reported to the host CPU, there is no assurance that another copy of the same data is recorded or available at that time. Thus, if such assurance is required, the CPU must wait for conclusion of recording of another copy, with a resulting performance penalty.